The present invention relates to phase-locked loop systems, and particularly those incorporating more than one phase-locked loop circuit.
Phase locked loop (PLL) circuits are well-known in the art. Initially they were very expensive to implement, and found use in only the most technically-demanding and/or cost-insensitive applications. However, as the cost of integrated circuit technology has decreased over the years, and as the performance capability of such integrated circuit technology has increased, PLLs are currently extremely inexpensive to implement and are found in wide use in many applications.
FIG. 1 is a block diagram of a traditional phase locked loop circuit 100 configured to generate an output signal having a frequency which is a multiple M/N of an input signal frequency. The PLL circuit 100 includes a phase detector 101, a loop filter 102, and a voltage controlled oscillator (VCO) 104. An input signal is conveyed on node 112 to a first divider 105, which generates a divided-down signal on its output node 109. The output of the VCO 104 is conveyed on node 106 to a second divider 103 which generates a divided-down signal on its output node 107. The phase detector 101 receives both the signal derived from the input, conveyed on node 109, and the signal derived from the VCO, conveyed on node 107, and generates on its output node 108 an error signal typically representing the phase difference between the two input signals. The output 108 of the phase detector 101 is provided to the loop filter 102, and the output 110 of the loop filter 102 is provided as a control voltage to the VCO 104. As is well known, other PLL components or different PLL components may be utilized in the phase locked loop circuit 100. For example, a phase/frequency detector may be utilized instead of a phase detector. Various loop filter configurations and VCO configurations may also be employed, as well as other types of controlled oscillators, such as current-controlled oscillators. Other variations are well known in the art.
Such a PLL may be susceptible to interference from external signals. While many kinds of circuits are also susceptible to outside interference, PLLs may be particularly sensitive because of their frequent use as a generator circuit for reference signals, such as clock signals in a digital system, and the unusually stringent stability requirements such use may impose. In FIG. 2, the VCO 104 of the PLL circuit 100 is shown again. An interference source 120 generates a signal on node 122 having a frequency f0+Δf which can couple (124) into the VCO 104 whose operating frequency is f0. Such coupling may be manifested as electromagnetic coupling, as power supply noise coupling from one circuit to the other, or as other forms of coupling. Such interference may be manifested as a clock jitter or clock phase noise on the VCO output node 106 which can degrade overall system performance.
Such PLL circuits used to generate a stable clock signal (e.g., a clock multiplying unit (CMU), a clock/data recovery circuit, etc.) may be designed to have a very low bandwidth in an attempt to provide a very stable clock output signal which provides high attenuation of any jitter of the input reference signal. But a PLL having a low bandwidth is more susceptible to interference than one having a higher bandwidth.
In many applications, the need to compromise the loop bandwidth may dictate a PLL whose jitter attenuation is less than desired and whose susceptibility to interference noise is greater than desired. Consequently, additional improvements are needed.